Field of the Invention
The disclosure relates in general to a three-dimensional (3D) stacked semiconductor structure and method of manufacturing the same, and more particularly to the 3D stacked semiconductor structure having one metal-oxide-semiconductor (MOS) layer formed between the stacking cells and metal routes to serve layer selection and method of manufacturing the same.
Description of the Related Art
A nonvolatile semiconductor memory device is typically designed to securely hold data even when power is lost or removed from the memory device. Various types of nonvolatile memory devices have been proposed in the related art. Also, manufactures have been looking for new developments or techniques combination for stacking multiple planes of memory cells, so as to achieve greater storage capacity. For example, several types of multi-layer stackable NAND-type flash memory structures have been proposed. However, the typical 3D memory structure suffers from several problems.
FIG. 1 is a perspective view of part of a 3D stacked semiconductor structure, in particular, a 3D NAND memory array structure. The 3D stacked semiconductor structure includes an array region 11 and a fan-out region 13. The multilayer array is formed on an insulating layer, and includes a plurality of word lines 125-1 WL, . . . , 125-N WL conformal with the plurality of stacks. The plurality of stacks includes semiconductor strips 112, 113, 114, 115. Semiconductor strips in the same plane are electrically coupled together by stairstep structures, also referred to as bit line structures. Stairstep structures (pad structures/bit line pads) 102B, 103B, 104B, 105B terminate semiconductor 10 strips, such as semiconductor strips 102, 103, 104, 105. As illustrated, these stairstep structures 102B, 103B, 104B, 105B are electrically connected to different bit lines for connection to decoding circuitry to select planes within the array. The stack of semiconductor strips 102, 103, 104, 105 is terminated at one end by the stairstep structures 102B, 103B, 104B, 105B, passes through string selection line (SSL) gate structure 109, ground selection line (GSL) 127, word lines 125-N WL through 125-1 WL, ground selection line GSL 126, and terminated at the other end by a source line (obscured by other parts of figure). The stack of semiconductor strips 112, 113, 114, 115 is terminated at one end by the stairstep structures (pad structures/bit line pads) 112A, 113A, 114A, 115A, passes through SSL gate 25 structure 119, ground selection line GSL 126, word lines 125-1 WL through 125-N WL, ground selection line GSL 127, and terminated at the other end by source line 128. A source line 128 comprises a stack of several insulating layer (ex: oxide layers) and conductive layers (ex: such as polysilicon as gate material) arranged alternately. A contact holes is formed vertically to the stack and filled with conductors for connecting each of the conductive layers to outer circuits.
However, it is hard to fabricate the SSL (string selection lines) islands as shown in FIG. 1. When the size of the 3D stacked semiconductor structure is scaled down and more layers and tight pitches are required, the process window is narrow.
Additionally, a PNVG structure, another type of the 3D stacked semiconductor structure, has been proposed, and the reverse bias leakage of PN diode is critically important for the PNVG structure to avoid boosted channel potential leakage. The PNVG structure needs sophisticated operation wave form during decoding to prevent PN junction leakage, and a three-phase programming method has been proposed. However, the programming method is complicated, and P+/N formation is not easy to implement.